Verification after Synthesis
نویسندگان
چکیده
The disconnect between sequential synthesis and sequential verification has two consequences: (1) strong sequential optimizations are not used during synthesis because they are hard to verify, and (2) verification, if performed in isolation from synthesis, borders on becoming intractable. This paper develops a scalable methodology for checking sequential equivalence of the original network and the network derived by integrated sequential optimization [15]. The method uses an “optimization history” describing the sequence of logic transformations carried out during synthesis. A format for representing optimization history is proposed and motivated. A preliminary implementation of the proposed methodology is described and experimentally compared with an efficient general-purpose equivalence checker that does not rely on information from synthesis.
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